As a GPU Design Integration Engineer, you will be responsible for:
BS + 10 years of experience.
Experience with Verilog/System Verilog.
Experience with the one of the following scripting languages: Perl/Ruby/Python.
Proficiency in logic design principles.
Ability to analyze architectural and micro architectural details to drive design partitioning.
Knowledge of PPA optimization techniques, Power Intent (UPF/CPF), CDC, RDC, synthesis, physical design and STA.
Experience with RTL analysis and/or PPA optimization using Invio, LEC and Genus.
Familiarity with GPU/CPU/SIMD Architecture and micro-architecture.
Ability to work well in a team and be productive under aggressive schedules.
Experience with scalable designs, design reuse, DFT insertion, LEC, Lint, codeline management, simulation and debugging tools.
Ability to debug and solve various design integration issues in a timely manner.
Ability to solve complex problems across multiple technical domains.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.