Nvidia Senior CAD Developer Timing Physical Design Optimization 

United States, California 

622475245

What you’ll be doing:

• Invent and optimize new methods for increasing chip frequency while minimizing power consumption across a suite of internal optimization tools. These tools already outperform the industry's alternatives in high capacity timing closure and will advance even further with your contributions.

• Improve algorithms (in C++) for gate-level sizing, buffering, useful clock skew, cell legalization, IR drop prediction, timing calculation, power minimization, ECO routing, and incremental parasitic extraction.

• As with any software engineering team, we do write a lot of code, but this is broader than a typical CAD or EDA role. Instead, we as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.

What we need to see:

• BS, MS, PhD in Electrical Engineering or Computer Science or equivalent experience

• Minimum 6+ years of relevant experience in CAD software and VLSI hardware design

• Strength in both CAD software and VLSI design

• Strong understanding of VLSI timing optimization and related concepts, including cell libraries, interconnect models, crosstalk, glitches, IR drop, timing constraints, corners, congestion, etc.

• Demonstrated ability in software development using C++

• Familiarity with design implementation tools such as PrimeTime, Tempus, ICC2, Innovus, and StarRC and typical design flows written in Perl, Tcl, and Python.

• Strong communication and interpersonal skills

Ways to stand out from the crowd:

• C++14 or newer experience, such as lambdas and concurrency

• Advanced understanding of timing modeling or P&R algorithms, such as CCS models, moment matching, incremental routing, cell legalization, etc.

• Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use, etc.