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Intel Global Yield Defect Control Manager GL Israel, South District 620750609
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Defect Control team managerresponsibilitiesinclude (but not limited to):
Build and lead Defect Control team in FSM HVM Global Yield organization to execute HVM yield roadmap.
Collaborate with Technology Development team and Process Integration team to import and setup new technology to production fabs across the globe.
Work with Process Integration teams, Yield Analysis team and FSM Yield managers to lead fast paced yield ramp-up in high-volume manufacturing phases.
Review, compare, and propose wafer inspection tool selection options in production line with comprehensive quantitative analysis.
Set up and optimize wafer inspection steps in process flow to ensure detection of yield detracting defects in line at step.
Design and execute production wafer inspection strategy to protect yield and quality at maximum productivity and lowest cost.
Build, maintain and update defect library per technology and per product.
Identify systematic defect issues and drive mitigation actions with Defect Reduction team in defined timeline to meet committed production yield targets.
Candidate should possess the followingbehavioral skills:
Problem-solving and project/program management experience with strong self-initiative and self-learning capabilities.
Demonstrated interpersonal skills to perform at leadership role including influencing, engaging, and motivating.
Proven track record of working across organization through matrix structures to accomplish strategic objectives with conflicting priorities.
Must demonstrate strong communication skills.
MinimumQualifications:
Master's degree in engineering or science area.
8+ years of experience in advanced node semiconductor industry in Defect, Yield, Metrology engineering or Failure analysis.
3+ years of people leadership experience to manage and direct an organization of 10+ process/defect engineers in fast-paced high-volume semiconductor manufacturing environment to drive yield, technology, quality, output and cost.
Strong understanding on defect mechanism and yield impact in semiconductor high-volume production and proven track record of driving down D0.
5+ years of experience with various defect inspection tools in high-volume semiconductor manufacturing.
5+ years of experience in wafer inspection recipe setup and optimization.
3+ years of experience in semiconductor high-volume production defect inspection line management.
In
addition:
Understanding on layout-sensitive defects and knowledge of scan diagnosis and other defect analysis skills.
Experience in FinFET technology development or high-volume manufacturing.
Working knowledge in module processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology. Skills to develop improvement projects at module level to improve process for reduced defectivity and improved yield.
Knowledge of module tool impacts to defects, inline parametrics and yield through PM life while understanding upstream and downstream impacts to other tools
PreferredQualifications:
Master's or Ph.D. degree in Physics or Materials Science major.
Experience in serving external Foundry customers through technical interactions.
Experience in GAA (Gate-All-Around) technology architecture and understanding on GAA-specific defect issues.
Experience in new semiconductor technology development.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.
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