Job DescriptionLooking for enthusiastic, motivated and self-driven engineer in area of
Power Analysis and Signoffwho can take care of
- Understanding and Defining Chip Power & Performance Targets
- Analyzing FSDBs for various design power scenarios and extracting the right activity windows
- Running Power Estimation and Analysis at block level and roll-up total power for SoC
- Working with Architecture, Design and Implementation teams for power optimization
- Running LP checks at block and full chip level, analyzing the logs/reports and deliver quality results
- Work closely with the FE & BE teams for overall Power Convergence and Low-Power Sign-off of the design for Tape-out
BE/ME in Electrical Engineering with 8+ years of experience in Logic Design, Synthesis and Low Power Design/Implementation for complex multi-million gate SoCs Expertise in power analysis using PT-PX/Prime Power Experience in Verdi tool for FSDB analysis Experience in power analysis using Power Artist tool is a plus Experience in industry standard tools LP checks, PTPX for power estimation etc. Strong analytical and problem-solving skills Expertise in Tcl, Perl/Python is requiredXeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.