Intel Graphic DFT Design Engineer 

Bolivia, Santa Cruz, San José de Chiquitos 

617980071

As a member of the Graphics Hardware DFT group you will be responsible for one or more of the following activities:

You will work on the design, RTL/GLS validation, automation and/or timing analysis in the following DFT domains: TAP Controller, Scan, Array DFT (PBIST/MBIST), IO DFT, PLL DFT or HVM Reset.
You will also contribute or be involved with trace pattern generation efforts as well as post-silicon enabling debug support and/or analysis of the DFT features and content types you are responsible for.

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Bachelors in Electrical/Computer Engineering or related field with2+years of industry experience. Or a Masters in the same fields with 1+ years of industry experience.
Your experience should be in any of the following:

• At least one of the key DFT features such as TAP/JTAG, Scan/ATPG or Array DFT (MBIST/PBIST)

• SoC IP DFT design integration or verification

• EDA tools such as ATPG tools, Mentor Tessent shell, VCS simulation and/or debug tools.

• Silicon enabling debug or test pattern development experience

Preferred Skills and Experience:

• Design automation skills and proficiency in programming or scripting languages

• Structural design flows, including timing, routing, placement or clocking analysis

• High volume manufacturing requirements and test flows

• 3D, media and display graphics pipelines

• SoC architecture

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits