Nokia SoC Frontend Design Engineer 

India 

617595980

We are seeking a skilled

Responsibilities:

• Develop RTL designs using VHDL/Verilog for FPGA/ASIC projects.
• Perform digital logic design, synthesis, and timing analysis.
• Conduct linting and static analysis to ensure code quality.
• Develop and implement verification methodologies (UVM, SystemVerilog).
• Create and maintain testbenches for simulation and functional coverage.
• Perform simulations and debugging to ensure design correctness.
• Participate in design reviews and provide feedback to improve design quality.

Essential Skills:

• Proficiency in VHDL/Verilog for RTL design.
• Strong understanding of digital logic design, synthesis, and timing analysis.
• Experience with linting tools and methodologies.
• Knowledge of FPGA/ASIC design and implementation.
• Familiarity with verification methodologies (UVM, SystemVerilog).
• Experience in testbench development, simulation, and functional coverage.
• Strong debugging skills to identify and resolve design issues.

Required Tools:

• Synopsys Design Compiler or Cadence Genus
• Mentor Graphics QuestaSim
• Spyglass VC

Desirable Skills:

• Experience with advanced verification methodologies and tools.
• Familiarity with high-level synthesis (HLS) tools.
• Knowledge of scripting languages such as Python, Tcl, or Perl for automation.
• Understanding of system-level design and integration.

Education and Experience:

• Bachelor’s Degree in Electrical Engineering, Computer Engineering, or a related field (Master’s preferred).
• 3+ years of experience in RTL design, digital logic design, and synthesis.
• Proven track record of successful FPGA/ASIC design projects.
  

Nokia has received the following recognitions for its commitment to inclusion & equality:

• One of the World’s Most Ethical Companies by Ethisphere
• Gender-Equality Index by Bloomberg
• Workplace Pride Global Benchmark