Western Digital Technologist ASIC Development Engineering 

Philippines, Quezon City 

613246507

Today’s exceptional challenges require your unique skills. It’s You & Western Digital. Together, we’re the next BIG thing in data.

The position requires BE/BSEE, or equivalent, with a minimum of 15 yrs of industry experience in designing Palladium/Protium & FPGA Platforms. The Position requires Bringing up Emulation Platforms Palladium & Protium & FPGA Prototyping hardware systems (HAPS) working closely with HW ASIC, System Validation & Firmware teams.

We are looking for experts in debugging & resolving Pre Silicon Prototyping issues working with FW/Validation with a mix of ASIC design porting skills to FPGA/Emulators & Prototype Bringup/Validation/FW Support Experience. This requires interfacing with ASIC Design/Verification & Validation/FW Teams to bring up the Pre Silicon Platforms.

Must have excellent communication skills, both written and verbal.

Technical expertise in Palladium/Protium Emulation & FPGA design for Xilinx UltraScale / UltraScale FPGA products is required. Should have work experience in bringing up Multi FPGA designs porting/mapping ASIC RTL to FPGA. Familiarity with Industry FPGA systems like HAPS FPGA Systems & ASIC Emulators and how to debug system level problems. Participates in all phases of the FPGA development life cycle, including requirements analysis, design, implementation, integration, and test of all products

Experience with industry standard interfaces such as PCI Express, USB, SATA, UFS, DDR4/5, I2C, UART, JTAG, High speed SerDes is required.

Experience in FPGA design methodologies including high speed design, serial protocols and FPGA timing closure is desired. Experience working on FPGA or Emulation is a plus.

RTL design knowledge using Verilog is required along with experience in using RTL verification tools and flows. ASIC Verification knowledge using various simulation tools is desired.

Experience with scripting languages like Perl, TCL C-shell is strongly recommended. Work experience in using Palladium & Protium Emulation Flow, HAPS-FPGA platforms / Synopsys Protocompiler flow & DINI FPGA Platforms / Synplify Pro is a strong plus. Experience debugging on Palladium/Protium Emulators is a plus.

Experience with lab bring up working on FPGA Prototypes is recommended.

BSEE + 15-18 Years experience or MS + 12-15 Years Experience
Work experience Palladium/Protium Emulation & FPGA Prototyping