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Google ASIC Design Verification Engineer India, Karnataka, Bengaluru 61218852
27.01.2025
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Minimum qualifications:
Preferred qualifications:
- Bachelor’s degree in Electrical Engineering or Computer Science or equivalent practical experience.
- 3 years of experience in the formal verification domain.
- Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog at Subsystem or Full chip level.
- Experience with scripting languages (e.g., Python/Perl, and TCL).
- Experience in formal verification applications (e.g., sequential equivalence checking, and connectivity checking) and data-path verification.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Science, or a related field.
- Experience working with one or more formal verification tools, such as JasperGold, VC Formal or Questa Formal.
- Experience with formal sign-offs of industry ASIC designs.
- Knowledge of formal methodology and formal abstraction techniques.
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