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Apple Design Verification Engineer United States, Texas, Austin 611451486
04.04.2024
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Key Qualifications
- Advanced knowledge of SystemVerilog and UVM
- Experience developing scalable and portable test-benches
- Experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations
- Experience with serial protocols such as PCIe or USB
- Experience with IP verification method
- Deep knowledge with IPs developments such as PHYs, PLLs etc.
- In lieu of UVM knowledge, C/C++ experienced level knowledge
- Excellent knowledge of one of the scripting languages: Python, Perl, TCL
- Proven knowledge of formal verification methodology
Description
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, DV environment bring-up, regression enabling all features under your care, and debug of the test failures. Develop block, IP and SoC level test-benches Track and report DV progress using a variety of metrics, including bugs and coverage. Develop IP simulation environment, and work closely with analog team to ensure overall bug-free IP design.
Education & Experience
BS degree in technical discipline with minimum 10 years of relevant experience.
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