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Apple CAD Design Verification Engineer Israel, Tel Aviv District 61054265
03.08.2024
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Description
You will Develop, maintain, and enhance an existing system for regressing RTL. Role involves debugging vendor tool problems.Interacting with Verification teams to help solve their problems. Implement new functionality to solve emerging problems or to optimize already existing methods.
Key Qualifications
- 5+ years of experience in Verilog and System Verilog
- Experienced with Synopsys VCS, NC-Verilog, or Models' - A must
- Strong scripting abilities in PERL are needed; TCL or Python is a plus
- Good communications skills are required and prior customer support experience is a plus
- Experience writing or maintaining the script or Makefile that builds the simulation Program from RTL is a plus. Familiarity with Verdi and/or DVE is considered a plus
- Knowledge at C and C++ is a plus
Education & Experience
BSc/ MSc in Electrical Engineering or Computer Science.
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