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Apple PMU Design Verification Engineer m/f/d Germany, Baden-Württemberg 608380634
19.09.2024
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Description
- You will develop verification plans in coordination with design leads and architects. - You'll be responsible for building and maintaining verification test bench components and environments. - Generate directed and constrained random tests. - Run simulations and debug design and environment issues. - Build functional coverage points, analyze coverage, and improve test environment to target coverage holes. - Craft automated verification flows for block and chip level verification. - Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM), and logic simulators to verify complex designs. - Work with other block and core level engineers to ensure a flawless verification flow.
Minimum Qualifications
- Bachelors in EE or related field, or equivalent work experience
- Excellent communication and interpersonal skills, combined with the ability to collaborate
- Ability to work well on a team, take ownership and motivate self and others
- Fluent English skills
Preferred Qualifications
- Sophisticated knowledge of SystemVerilog and UVM
- Experience developing scalable and portable test-benches
- Experience with constrained random verification environments
- Experience defining coverage space, writing coverage model, analyzing results
- Experience with Assertion Based Verification
- Good Knowledge of Object Oriented Programming
- Experience in Formal Verification (Formal Linting, Formal connectivity, user property verification)
- Experience with Python, Perl or TCL
- Good understanding of digital design and basic knowledge of mixed signal verification
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