As part of the verification team supporting Apple's Display Technologies portfolio for the next-generation of Apple products, you will work closely with Design and Architecture teams to review specifications and architecture, extract features and define verification plan including the coverage model. You will then execute on this plan through testbench development, directed/constrained random test generation, assertion-based verification, failure analysis and resolution, and coverage analysis and closure. You will run RTL and gate level functional simulations. You will also support mixed-signal co-simulation using Verilog models of analog IP, and develop testbench, test cases, reference model, coverage model and automation of regression suite. You will also have the opportunity to enhance the team’s methodology and flows.