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What you'll be doing:
Verifying the ASIC design, architecture, golden models and micro-architecture of a GPU unit using advanced verification methodologies such as UVM
Understanding the design, defining the verification scope, developing the verification infrastructure, and verifying the correctness of the RTL design
Collaborating with architects, designers, and verification teams to accomplish your tasks
What we need to see:
Bachelors or Masters Degree (or equivalent experience)
5+ years of relevant industry experience
Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies (UVM)
Experience with design and verification tools (VCS or equivalent simulator tools; debug tools like Verdi, Debussy, GDB)
Background in building testbench environments for unit level verification
Expertise in System Verilog and Verilog
Great communication and collaboration skills to interact within the team and across functional teams
Excellent debugging, analytical, and problem solving skills
Ways to stand out from the crowd:
C++ programming language experience and scripting knowledge is desirable
Experience with high-speed I/O verification is highly desirable
Experience developing and closing a detailed functional Verification Plan, ideally with some leadership responsibility for block-level verification
You will also be eligible for equity and .
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