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Google Silicon Networking RTL Design Engineer Google Cloud India, Karnataka, Bengaluru 602467149
10.03.2025
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL.
- Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).
- Experience in micro-architecture and design of IPs and subsystems in Networking domain such as packet processing, bandwidth management, congestion control, etc.
Preferred qualifications:
- Experience with scripting languages (e.g., Python or Perl).
- Experience in SoC designs and integration flows.
- Knowledge of high performance and low power design techniques.
- Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies.
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