Marvell Americas Benefits k Plan Analyst 

United States, California 

599372980

· Own and debug failures in simulation to root-cause problems · Work closely with Physical Design team for floorplanning, timing, power and area optimization. · Work closely with verification team for test plan development, debug, coverage closure and gate level simulations · Coach and mentor junior engineers of the team when necessary to achieve successful project outcomes.

What We're Looking For

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 7+ years of related professional experience. OR Master’s degree in Computer Science, Electrical Engineering or related fields with 4+ years of experience. • Experience with general digital design microarchitecture development. • Design/RTL experience in Verilog or SystemVerilog. • Knowledge of scripting languages, such as PERL, Python • Experience with high speed, low power, and area optimized designs. • Experience working with multi-clock designs, DFT, resets, LEC, Lint, etc. • Good learning, problem solving interpersonal and communication skills. • Must be a team player with a strong can-do attitude. • Self-motivated team player able to thrive in a fast-paced engineering environment.

Expected Base Pay Range (USD)

148,500 - 219,780, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at