Western Digital – ASIC Design Engineer 

China, Guangdong Province, Shenzhen 

594696991

Today’s exceptional challenges require your unique skills. Together, we can build the future of data storage.”

• You are responsible for the further development of concepts and methods for the EDA design environments with focus on analog / mixed signal ASIC design in advanced nodes.
• Solid understanding of PDK’s, effectively manage PDK libraries, collaterals and drive migration of design environments for incremental releases.
• Development of Calibre Physical Verification decks for CMOS PLANAR and FINFET technologies including DRC, LVS, PERC, FILL LPE and shape generation decks and scripts.
• Layout Automation and Utilities development in Cadence SKILL/SKILL++.
• Development and validation of PV tools and flows like parasitic extraction, EMIR drop and substrate noise analysis.
• Responsibilities will include testing, validation, customer support and new tool/methods evaluations, development of methods and procedures for quality improvement, automation of deck/techFiles generation and validation.
• Experience with Cadence custom IC Virtuoso platform to create layout test structures, to validate verification rules and to troubleshoot errors.
• Experience with physical verification tools for DRC, LVS and parasitic extraction, Calibre, starRC, ICV etc is plus.
• Working knowledge of revision control software (Git, Perforce, Subversion, Synchronicity, etc)
• Collaboration with the IT team to fulfil advanced nodes specific requests (Linux, Exceed-on-Demand, Grid, VMWare-ESX, Storage-system, etc.).
• Ensuring the operation and support within the CAD / IT-team for all ASIC designers worldwide.
• Managing the quality and ISO26262 requirements for the EDA tools, both for in-house developments and vendor products.

• Education: University degree (Master/PhD) in electrical engineering or a comparable subject
• Personality and working practice: communicative, problem-solving mindset, responsible, initiative, flexible and target oriented. Comfortable in working in a fast paced, dynamic environment with changing priorities.
• Experience and Knowledge: Minimum 10+ years of development experience of Mixed Signal CAD design Flows from Front to Back ,expert knowledge and experience of state-of-the-art design tools (EDA-vendors e.g. Cadence, Synopsys, Mentor) and Software-development-methodologies and tools (Linux, script- and programming-languages as well as Cadence Skill), thorough understanding of Custom Analog development flow, design tools and Software / Hardware environment
• Qualifications: ability to identify and analyse tasks efficiently within the scope of your work and to develop pragmatic application-specific solutions; pronounced ability to communicate, relevant experience in the methodology of problem solving as well as in the cooperation and leadership of international and cross-functional teams
• Technical Skills: Cadence SKILL, Calibre SVRF/TVF, Python, Shell Scripting.
• Languages: fluent in English written and spoken