Microsoft Principal Architect Memory Hierarchy 

United States, North Carolina, Raleigh 

594683036

As thein the silicon engineering organization, you will be a member of the team responsible for defining the overall SoC Architecture. You will work closely with the product and platform architecture teams, peer System on Chip (SoC) architects, IP architects, Performance/Modeling architects, Software (OS and Hypervisor) and Firmware architects, Design, Validation, and Execution teams, etc. to ensure our SOC and IPs enable performant, efficient, and industry-leading systems. The team you’ll be part of will be involved in numerous projects within Microsoft, developing custom silicon for a diverse set of systems. We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions in the most efficient manner.

Requirements:

• 9+ years of related technical engineering experience Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science.
• 7 + years of experience in SoC memory hierarchy/architecture, and contemporary as well as emerging memory technologies.

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications

• Understanding of I/O, memory subsystems, coherency flows, interconnect, and QoS mechanisms
• Understanding of computer architecture, SoC and system Hardware and Software architectures, and the associated tradeoffs
• Understanding of cache and memory controller architecture, micro architecture, and design
• Excellent communication, collaboration and teamwork skills and the ability to contribute to diverse and inclusive teams

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:Microsoft will accept applications for the role until July 29, 2024.

• Memory technology roadmaps including, but not limited to: DDR, LPDDR, HBM, Type 3 CXL-based Memory, RDIMM/MRDIMM, and emerging memory technologies
• Defining/driving the overall SoC memory hierarchy architecture from L3, L4, Main Memory, Memory Expansion, IO caching, and exploring alternative caching hierarchy/architectures
• Defining and driving the overall end-to-end Memory Hierarchy Quality of Service (QoS) architecture and microarchitecture (where appropriate) across hardware, software, and firmware
• Working closely with performance architects to define and drive modeling methodologies to enable memory hierarchy and QoS performance analysis and evaluation
• Working closely with memory controller architects and micro-architects to productize features
• Working closely with Strategic Planning and Architecture as well as internal customers to understand workload and use case requirements with specific focus on identifying full stack optimization opportunities within the context of the overall memory hierarchy
• Collaborating across teams to come up with the best solution possible with a One Microsoft mindset.
• Challenging the status quo with a growth mindset to push the envelope and enable world-class SOC products across Microsoft.

• Embody our