Amazon Software Development Engineer II Defensive Security 

United States, Texas, Austin 

590504922

Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity.The Role:
As CAD Manager you will be responsible for leading and optimizing the EDA environment for project Kuiper Digital and RFIC design teams. You will oversee the complete RTL-to-GDS flow, manage tool deployments, and drive methodology development across multiple semiconductor projects. This is an opportunity to shape the technical direction of critical IC design workflows and lead a team of skilled CAD engineers. You will advise on tools selection, and interface with various EDA tool vendors and foundries to run the EDA tools, PDKs and other files necessary for the Silicon Development Team to operate efficiently. You will be responsible for defining and creating a unified environment that sets the versions of the tools, PDK and design for every individual chip in development. Additionally, you will interact with the various Silicon development teams who will be requesting newer versions of the tools, and raise trouble tickets with CAD vendors as needed.Export Control Requirement:
Key job responsibilities- Establish and maintain standardized design flows and methodologies
- Develop Synthesis and Place and Route methodologies in process nodes for external foundries- Develop tools flows methodologies on digital back-end domains, APR, PnR, Synthesis Timing Physical and Electrical Verification LEC DRC LVS etc.- Build flow in TCL, Python to ensure quality and faster executions
- Understand different methodologies used across industry to adopt best practices

- Bachelor’s degree in Electrical/Computer Engineering
- Proven experience managing CAD teams and infrastructure
- 7+ years of silicon EDA and/or digital ASIC design experience

- Master’s degree in Electrical/Computer Engineering
- 10+ years of silicon EDA and/or digital ASIC design experience
- VLSI design with focus in synthesis place and route skills
- RTL2GDS including floor planning synthesis place route clock construction
- PPA Power Performance Area Optimization
- Layout timing LEC verification
- TCL, Python, PERL, or other scripting languages
- 2+ years in one or more of these tools: Design compiler, IC Compiler, Fusion Compiler, Cadence synthesis APR tool
- Physical aspect of VLSI designs
- Strong written and verbal communication skills.