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What you’ll be doing:
End-to-end verification from IP to Tegra/GPU full-chip for video and computer vision engines.
Embracing High-Level Synthesis (HLS) verification methodologies in addition to traditional ASIC verification.
Building block/IP testbenches based on the UVM (Universal Verification Methodology) framework.
Deploying advanced verification methodologies and infrastructure for SOC/IP.
What we need to see:
5+ years work experience
Bachelor's (BS) or Master's (MS) degree in Electrical Engineering, Computer Engineering, or related fields.
Familiar with verification methodology, tools, and flow.
Programming skills in System Verilog, Python/Perl, and C/C++.
Ways to stand out from the crowd:
Fully experienced verification flow: Know the typical milestones and the related verification action and release
Ability to use proper metrics to present and monitor verification status
Complex TB setup experience and skills below: SVA, functional coverage group, random constraint, etc.
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