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Job Description (Validator):
Defines and implements verification procedures (or test plans) for IP/Subsystem Hardware product based on features, requirements, and failure points.
Creates initial product verification methodology, selecting the verification strategy, identify failure points and developing test plans.
Develops verification environments and collaterals such as testbenches, stimulus/sequences, checkers, assertions, and coverage.
Performs tests regression, collects and analyzes regression results, root-causes and resolves regression failures.
Provides technical direction, guidance and support to the IP/Subsystem development team and stakeholders throughout the IP/Subsystem and customer's Product Life Cycle.
Influences on product development execution efficiency and quality through continuous improvement on verification methodologies and strategies used across product families.
Retrospect and explores new verification methodology or flow to improvise on existing ones.
Qualification :
Possess at least a degree in Electronics Engineering, Computer Engineering, Computer Science, or equivalent and experience with IP/SoC design or verification development.
Bachelors with at least 6 years' experience OR Masters with at least 5 years' experience OR Doctorate with at least 3 years' experience
Strong technical leader who communicates well with great influencing skills.
Strong analysis, debugging skills, and creative in problem solving.
Motivated, Self-driven and Independent.
System Verilog (OVM/UVM).
Coverage-based random constraint simulation.
Someone who wants to make a difference through technology while having FUN.
Additional Qualifications (Optional) :
Experience in any of these design tools and methodologies:
Scripting (Python/Perl/Shell).
Experience in PCI Express, SPI/eSPI/xSPI, AXI would be added value.
RTL simulators
Interactive debugger
RTL model build
Testbench development
Power-aware simulation = Scoreboard development
Experience in any of these areas: = NAND Flash or Storage Devices fields; Any industry standard device OR interface protocol
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