Broadcom Memory System Designer Place Route Engineer 

United States, Minnesota 

577943835

Job Responsibilities

• Architect and design memory subsystems

• Implement RTL of subsystem designs

• Place and route (physical design)

• Design closure: timing, DRC, LVS, EM/IR, etc.

• Gate netlist synthesis

Skill Set Required

• Strong design skills

• Ability to write and debug Verilog RTL code

• Place and route expertise

• Proficient in running STA, DRC, EM/IR tools, and attaining design closure

• Ability to code in Python

• Good understanding of synthesis tools and running synthesis

• Capable of running and debugging logical equivalency checkers

• Familiar with memory behavior

• Proficient in writing automation scripts, and tools savvy

• Good communication, interpersonal, and leadership skills

• Motivated, self-driven, and good at multitasking

Compensation and Benefits

The annual base salary range for this position is $107,000 - $171,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.