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Apple SoC Physical Design Verification Engineer United States, California, Sunnyvale 575153882
28.03.2024
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Key Qualifications
- Minimum BS.
- Strong knowledge of physical verification flows and methodology.
- Knowledge of all aspects of ASIC physical design.
- Scripting skills to debug flow related issues and make enhancements as appropriate.
- Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc.
- Real chip tapeout experience with a track record of successful signoff.
- Layout design background and experience a plus.
Description
• As a member of our physical design team, you will perform various types of physical verification checks such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography at the chip and block level.• You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout. • You will lead schedules and support cross-functional engineering efforts.• You will work on padring, bump, RDL design, and working with the package and floorplan teams.
Education & Experience
Minimum BS.
Pay & Benefits
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $55.82 and $84.09/hr, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
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