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Skills/Experience
2-6 years of experience in the design of complex ASICs
Strong expertise in RTL coding of complex designs using Verilog/SV
Exposure to low power design methodology and designs with multiple clock domains
Strong debugging, analytical skills and strong communication skills, both verbal and written
Hands-on experience in front-end design tools.
Minimum Qualifications
Bachelor’s or Master’s Degree in Engineering in Electronics, VLSI, Communications or related field
2 years of VLSI industry experience in Digital Design
Preferred Qualifications
Exposure to Bluetooth/BLE Technologies and scripting languages like Perl and/or Python
RTL Design, Linting Tools, Synthesis, Timing Analysis, Low-Power Design
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