Nvidia Layout Design Engineer 

India, Karnataka, Bengaluru 

559369641

ArchDev team. You will dive intoHSIO(High Speed IO -CXL/COU etc) and LSIO(Low Speed IO -etc) to make advancements in efficiency and stability for our GPU and SOC product. The SSG team is uniquely positioned to have an end-to-end view of the product development cycle - from early arch definition throughto product release. Ourarm is a hub for all silicon and system-level feature development, tradeoff analysis, system integration solutions, system POR alignment, validation, debug and tuning.

What You'll Be Doing:

• Proactively dive into new feature and spec from Pre-Si and lead test strategies development, including functional validation strategy, characterization and tuning methodology, platform/component interoperability, test design, debug capability and tools/scripts, system, SLT, and manufacturing test requirement.

• Lead IO new feature silicon bring-up, validation, and debug, and coordinate product schedule to release feature with high quality at aggressive schedule.

• Deep dive into technically challenging IO Pre-Si and Post-Si bugs andlead debugefforts across various teams(ASIC/FW/SW/PHY/board)to fix the issue on schedule and envision design optimization and collaborate with designer to implement for next generation.

• Proactively drive and identify opportunities and methods for test strategies and validation methodology optimization, efficiency improvement and innovation based on project learnings and challengings.

What We NeedSee:

• BS or MS degree in EE/CE or equivalent experience.

• 5+ years in silicon system architecture, digital design, validation, and debugging in HSIO, LSIO, PLL, Clocking and SerDes related areas.

• Depth in one or more areas of high-performance circuit SerDes and high-speed and Low-speed signaling, photonics, SRAMs, power delivery/regulation, security circuits, and high-speed logic).

• Strong understanding on protocol spec in HSIO (PCIE, CXL, USB) andLSIO (SPI/I2C/I3C/UART).

• Experiences on Power management and performance/power optimization, validation etc.

• Strong EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting.

• Excellent verbal communication and written, presentation skills.

• Deep understanding of firmware/driver structures and their interaction with HW.

• Working knowledge of PVT dependencies and binning methodologies.

• Experience with Python/perf etc script development, Windows and Linux OS is a plus.

• Effective in a collaborative environment.