Cisco DFT Engineer Design testability JTAG Scan BIST ATPG 7+ Years 

India, Karnataka, Bengaluru 

558578537

Be part of the development organization as an ASIC implementation engineer in Bangalore, India with a primary focus on Design-for-Test. You will work with Front-end RTL teams, and backend physical design teams to understand chip architecture and drive design for test requirements early in the design cycle. As a member of this team, you will be involved in creating groundbreaking next-generation networking chips. You will be led to drive the DFT and quality process through the entire Implementation flow with additional exposure to physical design signoff activities.

You are an ASIC Design DFT Engineer with 8+ years of related work experience with a broad mix of technologies including:

But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.)