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Who You Are
Your responsibilities are as follows but not limited to:
Designs, develops, and builds custom digital circuits for a CPU, including memory and caches.
Designs floorplans, performs circuit design, schematic entry, simulation for CPU blocks, and verifies functionality to optimize custom circuit for CPU power, performance, area, timing, and yield goals.
Creates block level DFT models, develops memory test tools, and improves and automates flows and methodologies to ensure streamlining of design.
Collaborates cross functionally to report design progress and to collect, track, and resolve any performance and CPU design issues.
Optimizes performance, power, and area, reduce leakage of CPU circuits, and drives characterization of individual memory instances and memory compilers.
Works with CPU architecture and layout teams to design circuit for best functionality, robustness, and electrical capabilities.
You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Bachelor's Degree in Electrical Engineering and/or Computer Engineering or any STEM related degree with 6+ years of experience in a high-tech company - OR - Master's Degree in Electrical Engineering and/or Computer Engineering or any STEM related degree with 3+ years of experience in a high-tech company - OR - PhD in electrical engineering and/or computer engineering or any STEM related degree with 2+ years of experience in a high-tech company.
2+ years of hands-on expertise and strong fundamentals in the following areas: Complementary MOS (CMOS) circuits design. Digital logic and optimizations. Circuit design trade-off for power, performance and area. Very Large-Scale Integration (VLSI). Low power implementation techniques. Memory design experience.
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