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Google Chiplet Technologist Design Integration Technical Lead Silicon United States, California, Mountain View 548375637
Yesterday
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, related field, or equivalent practical experience
- 8 years of experience in front end design
- Experience with SERDES IP integration such as PCIe, USB, D2D UCIe into SoC from feature definition to full design implementation
- Experience with standard bus protocols for interconnect design and with Tapeout of SoC or test chips in process technologies
Preferred qualifications:
- Experience with pre-silicon to post-silicon overall end to end execution
- Experience with post-silicon debug with the latest process technology nodes
- Experience with multiple foundries PDK design
- Strong statistical, data analysis, teamwork, and communication skills
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