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What you’ll be doing:
Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs
Collaborate with architects, ASIC designers, and verification engineers to design sophisticated system-level modules such as Floorsweep, In-silicon measurement, Reset and Boot controllers.
You will be responsible for the RTL design, logic synthesis, and timing analysis of several modules.
Integrate modules into the overall SOC design and work closely with other teams in the silicon bring-up process and ensure successful SOC level integration.
You will also use your expertise to identify and implement improvements in the current design flow and methodologies to improve efficiency and quality.
What we need to see:
BS / MS in Microelectronics/ Electronic Engineering/ Computer Science and related (or equivalent experience).
5+ years of ASIC design experience or SOC integration design / flow experience
Fundamental digital design concepts and experience in ASIC design flow including RTL design, verification, logic synthesis and timing analysis
Strong coding skills in Perl, Python, C++, or other industry-standard scripting languages
Basic understanding of verification methodology
Excellent analytical and problem-solving skills and attention to detail.
Ways to stand out from the crowd:
Familiarity with ARM CPU and SoC system architecture, microprocessor, and microcontroller fundamentals (caches, buses, memory controllers, DMA, etc.)
Experience with reset controllers, boot, fuse controllers or UCIe protocol
Hands-on experience in programming (C/C++) and scripting (Perl/Python).
You will also be eligible for equity and .
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