Intel SoC Design Verification Engineer 

India, Karnataka, Bengaluru 

537655781

Architects, develops and integrates layered Verification IPs, testbenches, testplans and test suite to validate the integrity and quality of Verification IPs and compliance with standards and SoC architecture & micro-architecture requirements.

Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and conform to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro-architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products.

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience.
• Related technical experience should be in/with: Silicon Design and/or Validation/Verification.

Preferred Qualifications:

• Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.
• Proficiency in UVM/SV constrained-random coverage based design verification.
• UVM/SV Verification IP architecture, development and validation experience.
• Robust understanding of fundamental principles of cache coherency in multi-processor SOCs, and experience with layered protocols - transaction layer, data link layer, and PHY layer.
• Experience with one or more scripting languages to facilitate automation.
• Strong debug skills and self-reliance in taking an issue to closure with internal and external partners. Takes ownership of assigned tasks.
• Keen problem solver, strong communicator, quick learner, effective team player and open to learning and teaching new and more efficient validation execution techniques to meet time-to-market.
• The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).
• Developing validation testbenches and test suites and driving continuous improvement into existing validation test suites and methodologies.
• Experience in Xeon CPU Pre-Silicon or Post Silicon Validation

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.