Job Description- Develops custom layout design of analog blocks, complex digital, mixed signal blocks, standard cell libraries, or memory compilers (e.g., bit cells, SRAMs, Register Files).
- Performs detailed physical array planning, area optimization, digital block synthesis, critical wire analysis, custom leaf, cell layout, and compiler assembly coding.
- Conducts complete layout verification including design rule compliance, SoC integration specs, electron migration, voltage drop (IR), selfheat, ESD, and other reliability checks.
- Uses custom autoroutes and custom placers to efficiently construct layout.
- Provides feedback to circuit design engineers for new feature feasibility studies and implements circuit enhancement requests.
- Develops and drives new and innovative layout methods to improve productivity and quality.
- Troubleshoots a wide variety of issues up to and including design and tool/flow/methodology issues used for layout design.
Qualifications- Candidate must possess a Bachelor's or Master's degree in Electronic/Microelectronic Engineering, Computer Engineering, or a related engineering discipline.
- 5 years of experience with physical layout design.
- Familiarity with Very Large Scale Integration VLSI and Complementary MetalOxide Semiconductor CMOS logic circuit design
- Proficient programming skills UNIX shell script TCL Perl.
- Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits