Qualcomm Senior DFT Engineer 

United States, California, San Jose 

525534679

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Preferred Qualifications:

• Minimum of 3+ years experience in the area of ASIC/DFT

• In depth knowledge of DFT concepts

• In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis

• Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations

• Expertise in scripting languages such as perl, shell, etc.

• Experience in simulating test vectors

• Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TK, TetraMax)

• Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus

• Ability to work in an international team, dynamic environment

• Ability to learn and adapt to new tools and methodologies.

• Ability to do multi-tasking & work on several high priority designs in parallel.

• Excellent problem solving skills

• Excellent communication and team work skills and good English is required

Principal Duties & Responsibilities:

• The person hired in to this role will be contributing to DFT insertion and validation effort of complex chip, core and/or blocks.

• Analyze, propose best compression that can be achieved for given SoC/core/block

• Own and deliver scan insertion, validate equivalence check

• Debug/resolve any DRC issues, identify solution and work with front-end team to ensure DFT DRCs are fixed.

• Analyzing and meeting ATPG coverage goals

• Owns STA constraints and work with STA team to resolve timing violations

• owns IDDQ constraints generation and validation

• Working independently in the team to solve problems, enable his team to deliver on time with high quality

• Responsible for deliverables of certain aspects of SoC DFT execution

• Responsible for pattern verification and debug

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range:

$143,000.00 - $215,000.00