Intel Graduate Talent Mixed-signal validation 

Malaysia, Penang 

522587214

Job Description

ISCP MIP MYS is seeking mixed-signal design engineer to join our talented and vibrant team. You will be directly involved in delivering next-generation DDR PHY designs for SOC application on Intel leading process node. Key Responsibilities include but not limited to

• Develop a Mixed-Signal Validation (MSV) testbench in accordance with the specified requirements.
• Own MSV for Custom Building Blocks (CBB) which covering open loop functional checks, closed-loop functional checks with RTL blocks, PHY level features, high volume manufacturing (HVM) features, closed-loop with Memory Reference Code(MRC) checks.
• Independently analyze the result based on specification documents and debug the root cause of the failures.
• Participate in MSV result review and collaborate with designers.

Qualifications

• Bachelor's or Master's degree in Electronics Engineering or related fields with minimum CGPA of 3.0.
• Education Focus should include integrated circuit design or RTL design.
• Highly analytical team player with a strong interest in debugging and problem-solving
• Strong written and oral communication skills
• Ability to operate independently and thrive in high-pressure, demanding environments.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits