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Broadcom Mixed-Signal Design Verification Validation Engineer 
United States, California, San Jose 
522249066

01.08.2024

Job Description:

Broadcom is looking for a senior level Mixed Signal Design Verification engineer. In this highly visible role you will be working on ASIC for data center connectivity applications.

Qualifications include:

  • BSc in Electrical Engineering or Computer Engineering 8+ years of experience in Mixed Signal Design Verification or MSc in Electrical Engineering or Computer Engineering with 6+ years of of experience in Mixed Signal Design Verification

  • Experience with system verilog and veriloga modeling of analog mixed-signal blocks.

  • Deep knowledge about real numbers, system verilog, UVM and verification coverage matrix

  • Experienced in developing checker, scoreboard & writing assertions.

  • Familiarity with analog mixed-signal building blocks such as ADCs, DACs, PLLs and SerDes.

  • Experience running mixed mode verification such as Spectre AMS Design and block level and chip level.

  • Familiarity with generating randomized vectors for analog and digital behavioral model verification.

  • Hands-on knowledge of standard industry EDA tools - Synopsys/Cadence.

  • Experienced with GLS with & without parasitic annotated simulations.

Highly Desired Qualifications:

  • Strong written and verbal communication skills, with the specific ability to speak to various technical and management levels.

  • Proactive, collaborative and creative approach to innovation, technical development and consensus facilitation to influence optimal project results.

  • Excellent time and task management, and interpersonal skills.

Compensation and Benefits

The annual base salary range for this position is $106,800 - $178,000.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.