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Google Design Verification Engineer Silicon United States, California, Mountain View 519515187
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 4 years of experience verifying digital logic at Register-Transfer Level (RTL) using SystemVerilog for ASICs or FPGAs.
- Experience verifying digital Intellectual Property (IP) and subsystems.
- Experience in Design Verification (DV) Testbenches/Environments.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience creating/using verification components and environments in methodology (e.g., Verification Methodology Manual, Open Verification Methodology, Universal Verification Methodology).
- Experience with verification techniques.
- Experience with scripting languages like Perl or Python.
- Familiarity with Application-specific integrated circuit (ASIC) standard interfaces (e.g., MIPI standardized interfaces, ARM AMBA interfaces, common low-speed peripheral interfaces like uart, i2c, etc.).
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