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Intel Senior Yield Modeling Engineer 
United States, Arizona, Phoenix 
508727832

20.05.2024

Senior Yield Modeling Engineer's responsibilities include (but not limited to):

  • Develop, maintain and update yield model to predict production line yield accurately in early stage of Si progression and deliver proposals to benefit production yield.
  • Develop new yield modelling methods and algorithms to deliver world class yield predictability and machine-learning solutions in high-volume manufacturing environment.
  • Collaborate with Data Science team to incorporate large-volume yield, defect, parametric and manufacturing data into yield modelling.
  • Track inline process and non-process changes to incorporate the changepoints into yield prediction model.
  • Develop yield models to identify potential parametric and defective loss components and support Process Integration, Device and Module teams to develop projects to eliminate systematic yield losses.
  • Collaborate with Process Integration, Device Integration and Defect team members to explore novel yield enhancement approaches and opportunities in high-volume manufacturing environment.
  • Engineering support for technical interactions with internal and external customers.

Candidate should possess the following behavioral skills:

  • Problem-solving technique with strong self-initiative and self-learning capabilities.
  • Ability to work with multi-functional, multi-cultural teams.
  • Must demonstrate solid communication skills.

Minimum Qualifications:

  • Bachelor's Degree in Electrical Engineering, Physics, Chemistry, Materials Science or in a STEM related Major
  • 5+ years' experience in advanced node semiconductor industry in data science and analysis / modelling.
  • Experience with exploring and identify product-specific yield/performance correlation from large amount of multi-level, unstructured fab data.
  • Experience with project DOI (Defect of Interest) kill ratio.
  • Experience in setting up yield projection modeling based on product yield and product layouts

Preferred Qualifications:

  • Advanced degree (Master's or Ph.D.) in Electrical Engineering, Physics, Chemistry, Materials Science or in a STEM related Major.
  • Experience with module processes including lithography, dry etch, wet etch, CMP, diffusion, implant, thin films and metrology.
  • Experience with defect scan methodology and yield loss
  • Experience in Python and other program languages to develop a new analysis method and algorithms using large amount of fab data. Expertise in big data analysis and machine-learning.
  • Experience in Device Physics and overall FinFET process flow.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits