Broadcom IP Integration Lead Engineer 

United States, Colorado, Fort Collins 

508062144

Job Requirements:

• A Bachelor’s Degree in Electrical and Electronic Engineering or equivalent and 8+ years of related work experience or Masters degree and 6+ years of related experience

• Understanding of design trade offs for power, area, and speed in ASIC designs.

• Understanding of complex issues related to timing closure, power integrity and signal integrity.

• Have a firm understanding of the ASIC design flow including FET design, RTL, synthesis, timing, floorplanning, power planning, P&R, LVS, DRC, ...

• Experience with Cadence Innovus or equivalent toolset.

• Strong verbal, written communication, and presentation skills.

• Team player that can easily work with different personalities and skill levels.

• Ability to multitask and manage multiple technical issues in parallel.

• Well organized, methodical, and detail oriented.

• Must develop, accurately track, and meet commitments to product engineering development schedules.

Desired:

• Experience with the Cadence Virtuoso design environment

• Experience or coursework with RTL languages(i.e SystemVerilog, Verilog, VHDL)

• Experience scripting in Skill, TCL, Ruby, Bash, Perl, Python, etc..

• Familiar with timing reports and strategies for fixing violations

• Experience or familiarity with Ansys Redhawk

Typical Duties Include:

• Develop a detailed understanding of Broadcom's die-to-die PHYs.

• Work and coordinate with multiple cross functional teams--analog design, digital design, physical composition, DFT, timing, and customers--to build PHYs

• Work with physical composition teams and interposer design teams to optimize signal IO patterns and escapes

• Work with analog and physical composition teams to optimize the size and power delivery to high IO density PHYs

• Work with teams to analyze power integrity (droop, EM, etc…) in various use cases and workloads

• Develop/writePHY integration documentationfor ASIC composition teams

• Develop list of Checklist task for integration of PHY IP into ASICS

• Work with IP build teams to complete quality crosschecks to ensure the quality of the PHYs

• Help support customer and ASIC PHY integration questions

Compensation and Benefits

The annual base salary range for this position is $107,000 - $171,000.

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.