The point where experts and best companies meet
Share
What you will be doing:
Be responsible for verifying the smartNIC designs, architecture and micro-architecture using advanced verification methodologies.
You are encouraged to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
Come up with test plans, tests and verification infrastructure for complex IPs/sub-systems.
Use advanced verification methodologies like e-specman, SV-UVM etc.
What we need to see:
BS (or equivalent experience) / MS
5+ years of experience in design verification.
Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).
C/C++programming/scriptinglanguage experience desirable.
Any Prior experience of smartNIC and/or high-speed interconnects.
Strong debugging, problem-solving and analytical skills.
Scripting knowledge (Python/Perl/shell).
These jobs might be a good fit