IBM PHY Verification Engineer 

United States, Texas, Austin 

505290700

Infrastructure is a catalyst that makes the world work better because our clients demand it. Heterogeneous environments, the explosion of data, digital automation, and cybersecurity threats require hybrid infrastructure that only can provide.

Your Role and Responsibilities
As a Verification Engineer, you will create test plans and testbenches to verify both logic and microcode provided by logic designers. You will communicate with our logic designers to create and review test plan documents and implement testcases from the document. Testcases are written in either cycle sim or event sim, depending on the application. Simulations should be randomized appropriately and executed in large numbers through batch submissions. Coverage should be collected and analyzed with the logic designer. Some amount of logic debug ability is expected.

Skills Needed:

• Testbench design, Automated testcase design (C++), Sim coverage collection and analysis, Batch submission and queue management, Randomization management,

Required Technical and Professional Expertise

• Experience with C/C++, SystemVerilog, UVM, Git, Verilog/VHDL, AMS verification, Linux OS, KornShell & BASH scripting, NCSim, Emulator, PSL
• Understanding of Analog circuits
• Familiar with C/C++, Verilog/Vhdl, System Verilog
• Experience with High-speed IO or Analog Mixed Signal Verification
• Bachelor’s in electrical engineering

Preferred Technical and Professional Expertise

• Familiarity with IO SERDES design, AMS verification, Mixed Signal Analysis, and design verification
• Exposure to industry microprocessor designs (e.g. x86, ARM or RISC-V processor design)