Microsoft Senior Test Engineer - Memory Subsystem HBM DDR SRAM 

Malaysia, Penang 

50486175

Required Qualifications

• 10+ years of experience in product and test engineering, specialize in ATE test program development
• 8+ years of experience in developing integrated circuits (pre-silicon, first silicon bring-up, new product introduction).
• 8+ years’ experience in large scale and/or high performance (i.e., AI, machine leaning, neural nets, CPU’s) and/or high power SoCs/chips on advanced process nodes.

Preferred Qualifications

• Strong presentation and communication skills.
• Knowledgeable in DFT and DFM techniques.
• Good understanding of bring-up/debug, characterization/manufacturing test (on ATEs).
• Advantest V93K experience is a plus
• Ability to drive development and bring up test content on mixed signal IP’s is a plus.
• Strong probability and statistics background including DOE’s.
• Experience in
  
  • Leading cross functional teams and understands program/project management.
  • Managing supply chain, vendors / partners, and Integrated Circuit production.
  • Experience in system/customer requirements gathering and interfacing.
• Device physics background.
• Experience with failure analysis, qualification, and yield analysis
• Trusted Computer architecture fundamentals/background
• Great unit/integration testing skills
• Fantastic Linux skills
• Background in debugging and optimizing software
• Adaptability (responds, explores, constructive attitude)
• Growth Mindset (It starts with a belief that everyone can grow and develop)
• Customer Focus (anticipates needs and proactively meets expectations)
• Drive for results (actively pursues outcome, delivers on commitments)
• Influence for impact (communicates, networks, persuades, influences)
• Judgement (scope problem, builds & applies knowledge)

Product and Test Engineering requires experience in end-to-end pre silicon and post silicon development which covers analog/digital test content development, debug, characterization, low yield debug, and test time improvement.

The position will have the following responsibilities:

• Expertise in specific/multiple ATE test module for Memory Subsystem which includes HBM, DDR PHY and SRAM.
• Develop pre silicon validation test plan (in partnership with design) and post silicon test plan for Memory Subsystem.
• Pre silicon simulation of Memory Subsystem test content usage model and how it gets integrated into ATE flow at wafer and package level.
• Developing Memory Subsystem ATE test methods and characterization for test modules.
• Analyzing test data to identify test program or silicon issues and working with cross functional teams to root cause will also be a focus.
• ATE level failure triage and debug across silicon, hardware, and software.
• Knowledge of system level tests and memory subsystem’s telemetry is a plus especially when dealing with System level test (SLT) failures and correlation of SLT with ATE test quality.
• Knowledge of platform, packaging, silicon power management and thermal is a plus and the ability to connect the dots will help in addressing any product quality issues.
• Experience in dealing with HBM supplier in areas of new technology evaluation, failure analysis, RMA and correlation work.

Making a difference

We fundamentally believe that we need a culture founded in a Growth Mindset. It starts with a belief that everyone can grow and develop; that potential is nurtured, not pre-determined; and that anyone can change their mindset.