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Cisco Senior ASIC Technical Lead United States, California, San Jose 503100041
27.01.2025
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The application window is expected to close on: February 10, 2025.
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
This role requires being onsite in San Jose, CA 4+ days/week.
Your Impact
- Development of high-performance designs/ASICs from specification to tape-out.
- Arch/micro-architectural definition and writing arch/micro-architecture specifications.
- Implement Verilog RTL to meet timing and performance requirements.
- Help define, evolve, and support our design methodology.
- Mentor junior engineers on performing project tasks and problem solving.
- Collaborate with the verification, PD, DFT, Package and SW teams to develop next generation AI Switching ASIC.
- Perform diagnostic and post silicon validation tests in the lab.
- Work with hardware and software teams to triage and root cause system, software, and customer failures.
Minimum Qualifications:
- Bachelor’s degree in Electrical or Computer engineering and 12+ years of ASIC Design experience.
- Experience with Verilog and System Verilog programming.
- Experience in architecture and micro architecture development.
- Experience delivering ASIC designs from specification to tape-out.
Preferred Qualifications:
- Master’s degree in Electrical or Computer engineering and 8+ years of ASIC Design experience.
- Experience in Data center/Hyperscaler/AI Networking technologies.
- Proven experience meeting and delivering project milestones and deadlines.
- Ability to communicate technical concepts to audiences spanning executives to junior engineers to customers.
- Demonstrated ability in troubleshooting and debugging.
- Scripting experience (Python, Perl, TCL, shell programming).
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