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Google ASIC RTL Integration Engineer India, Karnataka, Bengaluru 48730163
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
- 8 years of experience in high-performance design, multi-power domains with clocking.
- Experience in multiple SoCs with silicon success.
- Experience with Verilog or System Verilog language.
Preferred qualifications:
- Experience with ASIC design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF and Low Power Optimization/Estimation.
- Experience with chip design flow and an understanding of cross-domain involving DV/DFT/Physical Design/Software.
- Knowledge of one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing.
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