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Key responsibilities include:
Lead timing closure for sub-system/partition or full-chip level designs.
Collaborate with RTL, DFT, and IP teams to drive iterative timing feedback and closure.
Deliver timing collateral and signoff reports per project milestones.
Perform timing correlation between PD tools and signoff tools; support early feasibility studies.
Generate and push down ECOs to block-level teams.
Mentor junior engineers and provide technical leadership across teams.
Develop automation scripts in Perl, Python, and TCL to improve timing workflows.
Manage timing constraints compatible with synthesis, P&R, and STA tools.
What We're Looking For
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience. Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
Proven success in timing analysis and closure across multiple ASICs/SoCs.
Experience with advanced timing concepts: SI, CDC, LVF, POCV, etc.
Proficiency in STA tools (e.g., Synopsys PrimeTime, Cadence Tempus), scripting, and UNIX environments.
Strong communication skills and ability to work independently and collaboratively.
Lead timing closure across cross-functional teams, owning timing budgets, constraint development, and coordination with design, synthesis, and physical implementation to meet project milestones preferred.
Familiarity with timing methodology and flow development preferred.
Expected Base Pay Range (USD)
124,420 - 186,400, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
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