This is a specialized role which requires physical interaction with hardware equipment in a simulated data center environment, utilizing Google labs, power, and safety equipment. Regular development and processing of engineering hardware must be performed on site.
Minimum qualifications:
PhD degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
4 years of experience working in an ASIC or FPGA design technical environment, or 3 years of experience with an advanced degree.
Experience with Register-Transfer Level design using Verilog or SystemVerilog.
Experience in the FPGA/ASIC development lifecycle, including synthesis, timing closure, and logic simulation.
Experience with common hardware communication protocols such as Ethernet, PCIe, I2C, and SPI and common on chip system bus protocols such as AXI4, Avalon etc.
Experience with FPGA design and verification tools (Vivado, Quartus) and industry-standard simulation software.
Preferred qualifications:
Master's or PhD degree in Electrical Engineering, Computer Engineering, Physics, or a related field.
1 year of experience in technical leadership, leading FPGA projects or ASIC block development.
Experience with version control systems such as Git or Perforce for collaborative code development.
Experience with hardware and system design, and deploying and debugging hardware products in a large-scale data center environment.
Experience with server management technologies such as Data Center-Secure Control Module (DC-SCM), Low-voltage differential signaling Tunneling Protocol and Interface (LTPI), and system bootstrapping logic.
Proficiency with scripting languages for automation, such as Python or Tcl.