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Intel SOC DFT Lead/Manager India, Karnataka, Bengaluru 473250909
18.03.2025
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Job Description
- Client Development Group (CDG) is looking for an energetic, passionate, process-oriented Design for Test engineer to work on DFT RTL integration of Scan, TAP or MBIST features.
- Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).
- Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN).
- Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.
- Optimizes logic to qualify the design to meet power, performance, area, timing as well as design integrity for physical implementation.
- Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications.
- Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
- Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high-quality integration of the IP block.
- Direct responsibilities include RTL integration, quality related clean-ups (Unconnected, LINT, UPF, CDC etc), work with Front-end and Back-end design teams for hand-over.
- Bachelors in Electrical Engineering with 15+ yrs of experience, or Masters in VLSI with 10+ years of experience on related work.
- Good working knowledge of scripting language like Perl, Python is desired.
- Ability to drive overall DFX execution for an SoC is an added advantage.
- Minimum of 8 years in SCAN and TAP design.
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