3+ year experience in VLSI design of Processor Cores/SoC.
Familiar with advanced design practices (Clock/Voltage domain crossing and Low Power Design).
Strong Verilog/System Verilog skills
Familiar with CPU/ARM instruction set standard – an advantage
Familiar with the various backend tools (synthesis and STA) – an advantage.
Experience with scripting and programming experience using several of the following: Perl, C, Python, and TCL.
Familiar with verification methodologies – an advantage
Education & Experience
BSc/MSs in EE/CE
Additional Requirements
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