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Apple Design Verification Engineer United States, Massachusetts, Boston 463954469
06.06.2024
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Description
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to the following:Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring scalable and portable environment. Develop verification plans for all features under your care. Implement verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures. Develop block, IP and SoC level test-benches. Track and report DV progress using a variety of metrics, including bugs and coverage.
Key Qualifications
- Good proven understanding of System Verilog test-bench language and UVM
- Validated experience developing scalable and portable test-benches
- Shown experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations
- Experience with IP verification methodology
- In lieu of UVM knowledge, C/C++ knowledge
- Significant experience with DDR PHY/Controller and/or High Speed SerDes
- Deep knowledge of one of the scripting languages: Python, Perl, TCL
- Knowledge of formal verification methodology a plus
- Knowledge of UPF definitely a plus
Education & Experience
BS degree in technical subject area with minimum 10 years of proven experience.
Additional Requirements
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.
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