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QT Technologies Ireland Limited
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
About The Role
The EVA SOC delivery engineer would be required to liaise with IP teams across the geography and ensure timely delivery of these key image processing IPs to the SOC team. The candidate would be required to sanitize the RTL designs with respect to the various design rule checks before delivery to the SOC team for integration. With good expertise in scripting, the candidate would create innovative ways to run linting, CDC and other specific EDA tools on RTL designs to ensure compliance with various industry and Qualcomm specific design rules. The candidate would need to be an excellent communicator to build good relationships with the various IP teams to ensure timely reviews of reports generated by these tools, generating waivers, and fixing reported errors. The candidate’s role would be pivotal in meeting tapeout milestones.
Expertise in SystemVerilog and Verilog
Expertise in Scripting – Perl/Python
Expertise in Design rule checking – Lint , CDC (Clock Domain crossing), Reset synchronisation and Reset domain crossings, timing constraints verification.
Setup and run tools to sanitize IP deliveries from various teams. Review reports, fix errors, generate waivers
Expertise in Low power implementations
Strong knowledge of UPF/CPF fundamentals - set up/run tool, generate UPF, review reports, fix errors, generate waivers
Where you will be working
A gateway to Europe, Cork airport provides access to almost 50 international destinations including transatlantic air routes.
What's on Offer
Apart from working in an open, relaxed and collaborative space, you will enjoy:
Salary, stock and performance related bonus
Maternity/Paternity Leave
Employee stock purchase scheme
Matching pension scheme
Education Assistance
Relocation and immigration support (if needed)
Life, Medical, Income and Travel Insurance
Subsidised memberships for physical and mental well-being
Bicycle purchase scheme
Employee run clubs, including, running, football, chess, badminton + many more
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field.
*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
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