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1. Responsible for methodology enablement for memory blocks to meet over 5GHz Freq and low-power digital designs with optimal area.2. In depth understanding of different memory design concepts ((SRAM/RF/ROM).3. Expertise in Static timing analysis concepts.4. Close work with Layout and Floor planning teams.5. Back end design implementation of new features. 6. Expertise in Memory post silicon analysis.
7. Good understanding of statistical variation.
8. Planning, implementing and analyzing clock distribution from Full Chip level to leaf level for CPU cores.
QualificationsYou must possess a Masters Degree in Electrical or Computer Engineering with atleast 8 or more years of experience in related field or a Bachelors Degree with atleast 10 years of experience. Technical Expertise in synthesis, P and R tools preferred.
Preferred Qualifications:1. Digital Design Experience, with High Speed, Low Power.2. Familiarity with Verilog/VHDL. 3. Tcl, Perl, Python scripting.
4. Good understanding of spice simulations and analysis
5.Custom circuit design, IO design, full chip clocking6. Strong verbal and written communication skills.
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