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Apple Physical Synthesis CAD Engineer 
United States, California, Cupertino 
449635897

21.09.2024
Description
You will apply your hand-on skills in developing, improving and supporting the implementation flow from RTL through GDS signoff. You will be directly responsible to improve physical synthesis techniques through innovative scripts, flows and automation.Primary Responsibilities will include: - Develop and improve existing flows for Physical Synthesis and DFT Implementation - Work with tool vendors to resolve tool/flow issues
Minimum Qualifications
  • Experience with TCL, Python or Perl scripting languages
  • Knowledge of Logic design fundamentals
  • Experience with Synthesizable System Verilog RTL
  • Minimum requirement of BS + 0 years of relevant industry experience
Preferred Qualifications
  • Knowledge or experience with industry standard Logic Synthesis tools like Fusion Compiler or Genus
  • Exposure to static timing analysis and logic equivalence tools
  • Experience with writing synthesizable RTL code
  • Proficiency with TCL, Python or Perl scripting languages strongly preferred
Pay & Benefits
  • At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $58.61 and $88.29/hr, and your base pay will depend on your skills, qualifications, experience, and location.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.