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Job Description:
Broadcom is looking for a senior level high speed analog mixed-signal designer. In this highly visible role, you will be designing wireline high-speed analog mixed-signal circuitry for data center connectivity applications.
Qualifications include:
MS in Electrical Engineering or Computer Engineering with 10+ years of experience in CMOS high speed analog and mixed signal development in advanced technology nodes such as 7nm, 5nm and 3nm or PhD in Electrical Engineering or Computer Engineering with 7+ years of experience in CMOS high speed analog and mixed signal development in advanced technology nodes such as 7nm, 5nm and 3nm.
Experience in designing low jitter, low power PLL, VCO and clocking circuitry in advanced CMOS nodes.
Experience with analog and ADC based Clock and Data Recovery (CDR) is highly desirable.
Deep understanding of advanced clock distribution techniques such as resonant and traveling wave clocking.
Proficiency in electromagnetic tools like EMX or similar.
Understanding of high-speed optical and electrical interconnect architectures and design trade-offs to drive attainment on metrics such as power, jitter and timing budget.
Experience in assessing design bugs and recommending fixes or workarounds to balance technical requirements with schedule.
Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals.
Deep understanding of signal integrity and power integrity for high-speed designs.
Good understanding of design tape-out to foundries and solid understanding of supply chain for ASIC product development.
System knowledge of current generation and next generation of silicon photonics-based transceiver architectures and standards is highly desirable.
Strong analytical thinking and problem-solving skills with excellent attention to details.
Must be organized, self-motivated and able to work effectively across internal and end customers teams.
Must have excellent knowledge/experience with TSMC 7nm-5nm, i.e. understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, technology limitations.
It is desirable if the candidate has a good understanding of advanced packaging (2.5D / 3D) architectures.
Highly Desired Qualifications:
Strong written and verbal communication skills, with the specific ability to speak to various technical and management levels.
Proactive, collaborative and creative approach to innovation, technical development and consensus facilitation to influence optimal project results.
Excellent time and task management, and interpersonal skills.
Willingness to travel when required.
Compensation and Benefits
The annual base salary range for this position is $141,000 - $225,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
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